Systematic Generation of Executing Programs for Processor Elements in Parallel ASIC or FPGA-Based Systems and Their Transformation into VHDL-Descriptions of Processor Element Control Units

In this paper, a method for the systematic generation of the executing programs for the processor element of the parallel ASIC or FPGA-based systems liked to processor arrays is proposed. In this method, the each processor element of the array has separate control unit and is controlled in an autonomous way, based on the executing program received from the host computer before computations. This method allows: (i) to minimize executing program size stored in the processor elements; (ii) to make sizes of these programs independent from sizes of input data sets; (iii) to provide the independence of program contents from the realized applied algorithm; (iv) to derive the VHDL-description of all processor element control units in the behavioral style.